When a semiconductor device such as a metal-oxide-semiconductor field-effect transistors (MOSFETs) is scaled down through various technology nodes, high k dielectric material and metal are adopted to form a gate stack. In addition, a strained substrate using epitaxy silicon germanium (SiGe) may be used to enhance the carrier mobility. However, there is no strained engineering process correlated to circuit design optimization, especially in the epitaxy SiGe feature. Therefore, the epitaxy SiGe feature at an active region edge may cause mismatch issue and device performance degradation. Additionally, in the current device structure, the active region has a profile with a facet shape at the edge of the active region. The channel stress is decreased and the device performance is degraded thereby.